We would like to report a series of studies and prototyping for data acquisition for EIC experiments. The EIC data rate is estimated based on full detector Geant4 simulations, which define the strategy in the DAQ design. The DAQ architecture is based on a high-performance FPGA-based PCI-express DAQ interface, which bridges custom front-end and commodity computing. This series of interface cards have been developed for the FELIX DAQ in the ATLAS Phase-I upgrade and beyond, and it has already been adopted by many high-rate experiments in the 2020s. Prototype timing and flow control are used to synchronize all front-ends. The DAQ package, "RCDAQ", is already used by numerous EIC detector prototyping and beam tests. This work is closely connected with the on-going sPHENIX upgrade which supports both triggered and streaming readout at a higher signal data rate than that of the EIC. We welcome discussion, feedback, and collaboration on adopting this DAQ as part of the EIC detector R&D efforts.