18–22 nov. 2024
Collège Doctoral Européen
Fuseau horaire Europe/Paris

Survey of sub-electron noise CMOS image sensors

18 nov. 2024, 15:00
20m
Amphitheatre (Collège Doctoral Européen)

Amphitheatre

Collège Doctoral Européen

46 boulevard de la Victoire 67000 Strasbourg
15mOral Astrophysics applications Astrophysics applications

Orateur

Prayag Wakale (Caeleste and KU Leuven)

Description

Low-light imaging applications, such as astronomy or microscopy, require low-noise image sensors. Noise levels far below 1 $e^-_{rms}$ are pursued. Single-photon detection is considered the holy grail of image sensing.

Existing imaging technologies capable of detecting and resolving individual photons like Photomultiplier Tubes (PMT), Single Photon Avalanche Diodes (SPAD), and Electron Multiplication Charge-Coupled Devices (EMCCD) employ internal multiplication of the primary electron. Although these have sub-fractional $e^-_{rms}$ noise, these methods suffer from two performance-limiting properties: dark counts and excess noise.

This paper surveys solutions for photo charge integrating active pixel sensors (APS) and classic CMOS image sensor (CIS) technology. For integrating image sensor pixels to have quantum-limited photon detection, the readout noise at the pixel front needs to be substantially less than 0.3 $e^-_{rms}$ [1].

APS pixel separates the photo charge sensing and the charge to voltage conversion node. This results in a high in-pixel conversion gain and the cancellation of the kTC noise with correlated double sampling (CDS). The pinned photodiode in APS has benefits regarding dark current and rivals the charge-coupled devices (CCD) performance. Continuous improvement of CIS over the last two decades has led to the replacement of CCD by CIS.

In this survey, we review the publications that report a noise figure close to 0.3 $e^-_{rms}$ or lower. Based on the device and circuit techniques used and breakthroughs reached, we classify the publications into the following categories:

  1. Pixel circuit topologies
    • CCD-based skipper in CMOS [2][5],
    • Classic PPD-based pixel with source follower readout,
    • In-pixel capacitive trans-impedance amplifier (CTIA) [8], etc.
  2. Circuit operation techniques
    • Non-destructive readout [2][5],
    • In-pixel amplification [6],
    • Oversampling methods [2][4][8], etc.
  3. Device optimizations
    • Floating gate skipper in CMOS [2],
    • Reduction in floating diffusion (FD) capacitance [4][7][9],
    • Reset gateless pixel [4][7], etc.
  4. Transistor selection
    • Buried channel transistors [9],
    • Thin oxide transistors [4],
    • Standard transistors, etc.

At the conference, we will give an outlook on recent developments at Caeleste.

References
[1] N. Teranishi, Electron Devices, 2012
[2] Lapi, Agustin J. et al., TBD, 2024
[3] W. Deng et al., IEEE Transactions on Electron Devices, 2022
[4] A. Boukhayma et al., IEEE Electron Device Letters, 2020
[5] Stefanov KD et al., Sensors, 2020
[6] M. Sato et al., IEEE International Solid-State Circuits Conference, 2020
[7] M. Seo et al., IEEE Electron Device Letters, 2015
[8] Q. Yao et al., Proceedings of the International Image Sensor Workshop, 2015
[9] S. Wakashima et al., Symposium on VLSI Circuits, 2015

Auteur principal

Prayag Wakale (Caeleste and KU Leuven)

Co-auteurs

Bart Dierickx (Caeleste) Prof. Filip Tavernier (MICAS, KU Leuven)

Documents de présentation