Orateur
Description
In the development of hybrid pixel detectors, a reliable and cost-effective interconnect technology is paramount. This technology must be tailored to the specific pitch and die sizes of the applications at hand. Particularly crucial during the ASIC and sensor development phases, these interconnection technologies must also accommodate the assembly of single dies, commonly available from Multi-Project-Wafers.
Within the CERN EP R&D program and the AIDAinnova collaboration, innovative and scalable hybridization concepts are pursued for pixel-detector applications in future colliders. The recent focus has been on developing a reliable single-die interconnection process based on Anisotropic Conductive Adhesives (ACA). Two different approaches are studied: Anisotropic Conductive Paste (ACP) and Anisotropic Conductive Film (ACF). These ACA technologies replace solder bumps with conductive micro-particles embedded in an adhesive layer, applied either as film or paste. The electro-mechanical connection between the sensor and ASIC is achieved through thermo-compression of the ACA using a flip-chip device bonder. The ACA technology demonstrates versatility by also facilitating ASIC-PCB/FPC integration, offering a viable alternative to wire bonding or large-pitch solder bumping techniques.
A critical aspect of the ACA approach is the necessity for a specific pixel-pad topology, enabling connection via micro-particles and creating cavities for excess adhesive flow. This pixel-pad topology is achieved through an in-house Electroless Nickel Gold (ENIG) process, which is concurrently under development within the project.
The ENIG and ACA processes are rigorously qualified with various ASICs, sensors, and dedicated interconnect test structures, featuring pad diameters ranging from 10 μm to 140 μm and pitches between 20 μm and 1.3 mm. Thanks to recent process optimizations, an excellent ENIG plating yield has been achieved, with nearly 99% of pads correctly plated. For flip-chip assemblies using ACF and ACP, the rate of correctly connected pads is close to 98% for chips with large pad dimensions and pitches (80µm pads with a 200µm pitch). Current efforts focus on chips with pad dimensions around 10µm with a 25µm pitch, aiming to achieve similar connection rates for these smaller dimensions. Several projects participate with readout ASICs and sensors in the qualification of the assembly process, including Timepix3 with 12-14µm exposed pad diameter, 55 µm pitch on a 2cm² bonding surface, ESRF SPHIRD with 15µm exposed pad diameter, 50 µm pitch on a 5mm² surface, ALTIROC2/3 with 90µm exposed pad diameter, 1.3mm pitch on a 4 cm² surface, and CLICpix2 with 12µm exposed pad diameter, 25µm pitch on a 2.6mm² surface. The assemblies produced undergo comprehensive electrical characterization, including tests with radioactive-source exposures and high-momentum particle beams. Additionally, thermal cycling is conducted to study the robustness and potential aging of the assemblies. Initial results show good resistance of the interconnections to temperatures ranging from -40°C to 120°C.
In summary, this contribution serves to introduce the developed interconnect and plating processes, highlighting several types of hybrid assemblies produced and tested using the aforementioned methods. Notably, recent optimizations in plating and interconnect processes have led to improved plating uniformity and interconnect yield, enhancing the overall reliability and performance of hybrid pixel detectors.
