Présidents de session
Electronics
- Leonardo Rossi (INFN Genova)
We present the design and implementation of a comprehensive testing setup for validating pixelated detectors, emphasizing rapid prototyping and minimizing printed circuit board design and debugging efforts. The system features an off-the-shelf embedded controller with an Intel CPU running under LinuxRT, paired with an Artix 7 FPGA. This FPGA supports both VHDL and LabVIEW code, enhancing setup...
The ITkPixV2 readout chip is the production readout chip for the ATLAS Phase 2 upgrade for the High-Luminosity LHC of the ATLAS inner detector, scheduled for commissioning at the start of 2029. The innermost layers of the ATLAS ITk pixel detector are expected to reach maximum hit rates of 3GHz/cm^2, a total radiation dose of 1 GRad, and data readout rates of 5Gbps, with an operational lifetime...
The LHCb Upgrade-I detector is currently operating at the Large Hadron Collider at CERN and it is expected to collect about 50 fb−1 by the end of Run 4 (2032), when many sub-systems of the detector will reach their end of lifetime. In order to fully exploit the High-Luminosity LHC potential in flavour physics, the LHCb collaboration proposes a Phase-II Upgrade of the detector, to be installed...
