18–22 nov. 2024
Collège Doctoral Européen
Fuseau horaire Europe/Paris

Timing performance of a digital SiPM prototype

21 nov. 2024, 11:07
17m
Amphitheatre (Collège Doctoral Européen)

Amphitheatre

Collège Doctoral Européen

46 boulevard de la Victoire 67000 Strasbourg
12mOral Timing with pixels Timing with pixels

Orateur

Daniil Rastorguev (DESY)

Description

Single Photon Avalanche Diodes (SPADs) have been recently introduced in process design kits of several CMOS foundries. This opens up possibilities to embed SPADs into custom CMOS ASICs, thus allowing for novel designs of monolithic silicon avalanche photo-detectors. A digital silicon photomultiplier (dSiPM) prototype with integrated readout was designed at DESY in the LFoundry 150 nm process node, featuring a matrix of 32x32 SPAD pixels, each including four 25 µm SPADs and signal processing circuits. This device combines the intrinsically fast rise time and single-photon detection capability of SPADs with features typical for pixel detectors, such as full hitmap readout and individual pixel masking. To match the fast rise time, the dSiPM provides fine hit timestamping (bin size of 95 ps) with on-chip time-to-digital converters.
The dSiPM, simultaneously offering excellent timing resolution due to the use of SPADs as sensitive elements, and also good spatial resolution thanks to the high-granularity readout, is an interesting candidate for a 4D-tracking detector in future collider experiments. As a 4D-tracking device needs to provide time and position information for each individual particle interaction, uniformity of timing characteristics across the sensitive matrix is of particular interest.
This contribution focuses on the characterization of the temporal resolution of the dSiPM prototype, performed by the means of charge injection with a pulsed laser and by the direct detection of charged particles at the DESY-II test beam facility. Measured timing characteristics match the design expectations, and their variations as a function of the interaction position can be correlated to intrinsic SPAD properties, and to the layout of the digitization circuits.

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