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Bat 20 - uElec (https://cern.zoom.us/j/69600555186?pwd=eVcxUTBnc2J0bWwyQ3RBM0ttZkN6Zz09)
Bat 20 - uElec
https://cern.zoom.us/j/69600555186?pwd=eVcxUTBnc2J0bWwyQ3RBM0ttZkN6Zz09
* Discussion on CE-65++, Andrei, Szymon
o general trend is to stick to our initial plan (see Andrei's slides from 2021/07/21 in timetable) with same matrix size and pad for the various circuits
- of course biases will be different
o Three classes:
- C: analogue with rolling-shutter => dedicated to charge collection properties
- A: analogue output with FE from digital pixel => dedicated to digital amplifier properties
- D: digital output with FE from digital pixel => dedicated to digital amplifiers study & digital cluster performance
o Class analogue output with rolling-shutter (CE65v2_C)
- nb of versions (i.e. chips) depends on tests and MOSS choices (see discussion in talks on 22/07/2021)
- MOSS pixel pitch are now 18 um with square arrangement & 22.5 um with staggered arrangement
- a single front-end should be chosen from the 3 versions in CE-65 (SF-DC, Amp-DC, Amp-AC) from current tests
* probably AC is probably not favored by CERN
!! we should pay attention nb of versions due to our limited test abilities
- important versions: 15 um square for reference / 18 um square / 22.5 um staggered
* 15 um square we have already in CE-65, only important if something (epi layer, FE, coupling is changed)
* we should also consider having square and staggered version for the same pitch => 18 um hex?
- other pitches or arrangement with lower priority: 18 um staggered / 22.5 square
- minimum 3 chips, could go up to 5
o Class analogue output from the FE used in MOSS digital pixel (CE65v2_A)
- read-out uses rolling-shutter + analogue multiplexer
- select one single pitch, like 18 um square
- possibly various types of amplifier
* the amplifier version should be discussed and shared with CERN
* may have one chip per ampli version or combine various ampli versions in same chip (depending on # version)
- typically 2 or 3 chips
o Class digital output with the FE used in MOSS digital pixel (CE65v2_D)
- exact same version of FE as CE65v2_A
- possibility to have at most 2 different pixels: 18 um square (baseline) + 22.5 um staggered
* having another smaller pitch would be interesting for position resolution but sounds difficult
- pixel includes a discriminator and a memory or latch for read-out
* possibility to have same read-out with one single difference between class A and D
- typically 2 chips
o Each chip could have various types of sensing node config: std, blanket, gap
- seems worth to have the 3 options for each class
o Count of chips
- from 6 (only highest priorities) to 9 versions to be multiplied by 3 sensing node configuraionts => 18 to 27
- still possibly 3x splits
==> discussion summarised in Christine's table present in timetable
* MOSS design, Fred
o about newly available metal layers, still under discussion wrt timeline
- indeed using the new metal stacks will generate modifications hence delay
o DAC version and tests (Isabelle, Szymon): report required by CERN, executive summary being prepared by Szymon
o otherwise, not much news, targetting completed version for end of November
* MOST design, Szymon
o still target fully designed and functional version, even if not final, for end of November
* Tests of CE-65 from MLR1, Serhiy
o since last Friday, system is working with 2 chips (B-1, A-1)
- need to adapt more carrier-board equipped with sensors!
o first signals observed but investigation on-going
=> urgent need of analysis sw (TAF in preparation by Jerome)
* NEXT MEETING: Thursday November 25th
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