Europhysics Conference on High-Energy Physics 2011

FF-LYNX: project status and perspectives

Non programmé

1m

Dauphine (Alpes Congrès - Alpexpo)

Poster Detector R & D and data handling

Orateur

M. Guido Magazzu Magazzu (University of California Santa Barbara (UCSB) / INFN-Pisa)

Description

In future High Energy Physics experiments severe power and radiation hardness requirements and non-homogeneous latency and bandwidth constraints in data transfers from Front-End electronics to remote trigger processors and readout systems will push toward “standard” and flexible protocols and modular architectures. The use of IP-cores available to ASIC and FPGA designers will contribute to meet these requirements with reasonable development and production costs. The FF-LYNX protocol was initially proposed in 2009 to allow physical serial links and interfaces to be used for both the distribution of Timing, Trigger and Control signals and the Data Acquisition, leading to a significant reduction of the amount of physical links and overall material budget. In this protocol two channels multiplexed in the time domain are used for triggers, frame headers and synchronization patterns, protected by a robust encoding against transmission errors, and data frames. The protocol supports “Fixed Latency Frames” for high-priority information, as data to remote trigger processors, and “Variable Latency Frames” for data with no bounded latency. A key feature is the flexibility with respect to bandwidth requirements, allowed by the different speed options: 4xF, 8xF and 16xF (F = frequency of the reference clock frequency; F = 40MHz in the LHC). The protocol has been implemented in radiation tolerant interfaces to serial electrical links, with parallel ports to host devices. Receivers have flow control to minimize losses when host devices are not ready to data transfers. The interfaces are currently compatible with “double-wire” electrical links, but in the future “single-wire” links with clock and data encoded onto one serial line will be developed to increase reliability in high speed and long physical connections. Prototypes of the interfaces have been designed as IP Cores in the IBM 130nm CMOS technology and embedded in a test circuit submitted for fabrication in February 2011. This technology provides intrinsic radiation hardness against Total Ionizing Dose while Single Event Effects are mitigated by the adoption of Radiation Hardening By Design (RHBD) techniques. The potential benefits of the FF-LYNX protocol and interfaces for our community will be described in detail as well as the project status and perspectives.