Orateur
Description
The demand for deterministic, low-latency timing control at Los Alamos Neutron Science Center (LANSCE) has driven the integration of Event Receivers (EVR) with embedded Linux environments. We present an open-source Field Programmable Gate Array System on Chip (FPGA SoC) platform built with Yocto for the Xilinx ZCU102 UltraScale+ MPSoC. The MPSoC hosts an embedded Linux kernel and the EPICS input/output controller (IOC) framework. LANSCE development uses the Microresearch Finland (MRF) open-source EVR, which handles the deterministic tasks in the FPGA, and the mrfioc2, a register-level abstraction for open EVR. To meet LANSCE specific timing requirements, we are integrating an existing IOC that operates with MRF's EVR-230. The MPSoC will handle timing beam data and move pulser widths and delays to the appropriate registers within 3mS. With EPICS channel access over Ethernet, this platform will demonstrate interrupt handling in an embedded Linux environment. The reproducible Yocto builds and modular kernel module development will facilitate ongoing integration and customization of the timing infrastructure to LANSCE's evolving needs.
LA-UR-26-22138