65 nm meeting

→ Europe/Paris
Bat 20 - uElec (https://cern.zoom.us/j/69600555186?pwd=eVcxUTBnc2J0bWwyQ3RBM0ttZkN6Zz09)

Bat 20 - uElec

https://cern.zoom.us/j/69600555186?pwd=eVcxUTBnc2J0bWwyQ3RBM0ttZkN6Zz09
Cacher
  • Beam test analysis, Yitao, Ziad
    • issue on alignment along Y axis, shift appears (not present in X)
      • strangely the effect change sign for A4 (std diode) and B4 (modified diode)
      • current alignment done with a cut on all pixels SNR>10 => no shift observed here
        • shift in Y is observed when the residual is drawn for clusters defined with seed_charge>100e-
        • interpretation: shift appears in Y because it is the read-out direction
      • will try with the same cuts as for the final analysis (seed_charge> 100, 200, 300 e-)
    • issue on efficiency
      • the exclusion of 2 pixels on the edge was applied on DUT on individual ROI (sub-matrix)
      • in the process of correcting this
    • local installation of Corryvreckan (Ziad)
      • issue with library compatibility between EUDAQ-libs and PYTHON-3
      • trying to solve this with PYTHON-2
      • Yitao offers to try the installation on one of our machine

 

  • MOSS design, Fred, Xiachao
    • abstract generation on-going (Fred)
    • matrix timing characterisation (with Liberty tool for digital cell) on-going (Xiaochao)
    • both activities should be closed shortly (unless surprise)
    • submission prospect: no update, deadline for designers still end-of-July

 

  • CE-65v2, Andrei
    • cross-check on-going by Isabelle & Szymon
    • additional design rules received from CERN => Szymon checked some of them, on-going
    • About fast discharge observed in heavy irradiation
      • gets somewhat better by cooling down to 6 degrees & using fast read-out
        but only for limited # columns => difficult to study charge-sharing at such high fluence (1e15 neq/cm2)
        => might be good enough for lower fluence like 1e14 neq/cm2
      • proposal to change the read-out for V2, with an additional option
        => Walter thinks it is very difficult for ER1, not enough time
      • the proposal should be kept for V3 in ER2

 

  • Read-out architecture study, Jean
    • read-out under study = Dynamic Priority Arbiter (instead of the current Priority Encoder)
      • asynchronous logic
      • succession of individual arbiters (inputs = 2 previous arbiters, output = next arbiter)
      • present implementation is TPA for
    • ongoing: layout & model of the C-gate needed to build the arbiters

 

==> NEXT meeting July 13th

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