SiW-ECAL technical meeting

Europe/Paris
Vincent BOUDRY (LLR - CNRS, École polytechnique/IPP Paris)

Technical Meeting

Participants:

R. Poeschl, V. Boudry, A. Gallas, A. Thibault, J. Nanni, Y. Okugawa, J. Maalmi, D. Breton, Remote: A. Irles, J.C. Brient, D. Jeans, T. Suehara (10–11), J. Jeglot

Note: the TODOs are marked with [ ] followed by initials (F.L. for Firstname Lastname)

 

Introduction – Vincent

See attached preliminary plans, version 6a

  • [ ] V.B. “ to be updated according to the outcome of the meeting
  • No BT at CERN 2026–mid2028.
  • Maybe no BT at DESY 2026–2027 (depends on funding of PETRA IV).

ASIC testing – Vincent

Same status as presented at the CALICE meeting 28/03:

  • ~460 ASICs avail.
  • Test bench in Ωmega; program from Stephane; 9 mins / ASICs
    • ~13 scan performed in 9 mins;
  • 46 with NOVAPAC tested:35 OK, 3 “OK but”, 8 BAD–TBC
  • 105 with NPAC tested: 85 OK; 44 “OK, but”; 6 to be rested; 3 BAD
  • Full Text file recorded but not yet analysed
    • A bachelor student will continue the analysis ≥ 26/06

PCB

Production – Jérôme

30 PCB produced and received (last 10 in IJC)

If possible, PCB handling with gloves to avoid finger grease.

  • [ ] Not done for metrology ?
  • Jihane : Not practical for electronics testing. A support is needed, see discussion in " How to handle the ASUs ?"

Note: a cleaning is done (washing machine ?!?) after the cabling.

A cold plasma washer is now available in IFIC.

Inventory ?

PCBs are identified by a number on the technical sides;

To be replaced by a sticker when the sides are removed.

Added by V.B. after the meeting:

  • [ ] WHO is providing an inventory and measurement DB of the PCBs ?
    • in the DB:
      • PCB number; slab number
      • ASICs numbers
      • Metrology
      • Sensors number
      • Unique ID from the Texas chip

Metrology – Alice & Alexandre

  • 4 PCB measured in IJC using a sensor head in 1 afternoon (⊃ explanations) by a mechanics operator. Usually used to check the tooling.
    • Only for flatness; not for lateral dimensions
    • [ ] A.T.: data to be looked at
  • Metrology of cabled boards in next days ?
    • [ ] not on a day notice; A.T. will ask

Cabling - Dominique

  • Cabling of 4 PCBs will proceed this day 12 juin 2023
    • Delay due to missing component; ordered and delivered
  • 💡 R.P. : have ≥ 2 boards in each lab (IJC, LLR, IFIC). ➞ launch cabling of 2 others as soon as 4 tested OK.
    • ☝️ J.N.: LLR can wait for the 2nd prod, as no manpower yet available for testing.
    • ☝️ A.I.: Same for IFIC, BUT at least one board needed for dimension checks of the gluing support.
    • [ ] WHO : Send 2 at IFIC ≤ 14/07 See Logistics

Testing – Jihane

  • Fast testing only: 1 week ➞ end of June
    • In-depth testing later, DAQ needs some adaptation (see DAQ)
  • Does require a support to manipulate the boards + SLBoards
    • see discussion in How to handle the ASUs ?

Kaptons – Jimmy, Jérôme

The Kaptons thickness were measured : ???

10 pieces of Kapton v5 are available.

Pre-folding

There was an error in the folding by 1 mm (towards the center of the wafers). Flattening + refolding is risky for the copper layer.

For one of them, direct folding with the bord in a U worked fine (Jérôme).

Production of Kapton v6 can be launched as soon as we are sure about the design.

  • [ ] Jimmy+Jérôme: what test are needed to be sure ?
  • [ ] R.P. Funding ? AIDAInnova or SE2024 ?

Sensors

Inventory

  • [ ] to be (re)done in each lab
  • IJC:  12 Wafers from 2020, stored under controlled conditions.
  • LLR: ?? 

Testing

  • [ ] A.I.: Contact EVA and Jan Benhammou to see who can make the design of the testing PCB.
  • [ ] J.N. Alternative: Rémi @ LPNHE ? ➞ will discuss DRD6 soon.

Gluing

Robot and Clean room – Adrián

  • “clean” room ready in September ⊃ robot
  • 3 samples of glue tested
  • Test of conductive + mechanical glue dots not advised by expert (≠ curing time, mixing, etc.)
  • Dummy wafers (by PhotonExport, Spanish importer ?) costs ~ 55€/pce
    • Mail from Adrián:
    • Si wafer coated with Aluminium
      Material: Si
      Diameter: 2 inches mm
      Type: P
      Dopant: Boron
      Orientation: (100) +/- 0.1º
      Thickness: 300 um +/-25 um
      Resistivity: < 10 Ohm.cm
      Surface Finish: SSP
      Coated Layer: 300 nm Al
  • Conduction tests done on LUXE-type “flex PCBs”
  • Test on “standard” double face tape to come…

Underfill – Alice & Alex

  • A very fluid epoxy glue (designed to fix the BGA circuits) fills all the space between the wafers and the PCB,
  • by capillarity from one side of the ASU, it “ramps up” the PCB-Wafer space.
    • This gap must NOT be > 200 μm.
  • Applied after the conductive glue dots.
  • It stops by itself of at the borders of the wafers & PCB, and will not go through the inter-wafer gaps. Tested on LPNHE test PCB+Glass samples.
  • To be done:
  • [ ] A.G+A.T. : calibration of the polymerisation time
  • [ ] A.G.+A.T.: Calibration of the amount of glue
  • Traction tests :
    • [ ] A.G.: Mail to LLR (Antoine Cauchois cauchois@llr.in2p3.fr) to see availability of the equipment
    • [ ] A.G. + Alice: find a good traction test design.
  • [ ] Possibility for A.G. + A.T to go to Valencia ?

SLAB and Casing

How to handle the ASUs ?

  • “Old” U might do it for electronics tests and handling
    • [ ] A.T. : should be cleaned up (rest of glue ?)
  • Buffers (”cale” in French) have to be designed to compensate for the difference of thickness between the PCB (or ASU) and the SLBoards with its underside components
    • 1 buffer for PCB and another one for ASUS (=PCB+wafers+Kapton)
    • [ ] A.G. : Remeasure all the thicknesses, check the compatibility with the existing structure.

Structure

A priori, no change on the existing structure, if the thicknesses of the SLAB are OK.

We keep the same thicknesses of W.

  • Modifications
    • SLBoard modification ( "simple" replacement of 1 power-supply component by a wire )
    • DAQ adaptation for reading of the probe
    • Handling of the Texas ID + temp monitoring
    • [ ] D.B. Can the pins of the SLBoard below the card be shortened ?
    • [ ] D.B.+J.M. How many spares ? 3 ?
    • [ ] J.M.: send a SLboard to IFIC with the PCBs
  • New SLBoards:
    • Production dependent on availability of MAX10 FPGAs, will be delivered in December !
  • Adaptation to several ASUs (for next years and for the Long Slab)
    • already implemented for but needs to be X-checked
    • [ ] J.M. Tests for 2 ASUs
    • [ ] J.M. Adapted for ≤8 ASUs (added by V.B.)

Assembly & commissioning

NO ONE is available now to do the commissioning.

  • [ ] Need to find a master commissioner !

BT preparation, planning, analysis

Plans in Kyushu

Taikan will move to Tokyo in Autumn.

The material will be shipped in August.

AoB

Logistics

To be organised :

  • 💡 added by VB: keep inventory

PCB casing:

  • Could be sent with standard electronics cardboard box filled with honeycomb foam.
    • [ ] J.N., J.M. : Availability ?

ASU Casing, 2 examples:

  • HGCAL:
    • [ ] R.P. contact Eva to learn more
    • [ ] J.N. contact Rémi to get reference of the “old” plastic boxes.
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