65 nm meeting

→ Europe/Paris
Bat 20 - uElec (https://cern.zoom.us/j/69600555186?pwd=eVcxUTBnc2J0bWwyQ3RBM0ttZkN6Zz09)

Bat 20 - uElec

https://cern.zoom.us/j/69600555186?pwd=eVcxUTBnc2J0bWwyQ3RBM0ttZkN6Zz09
Cacher
  • Test beam data analysis, Yitao
    • all program covered, except for the irradiated sensors (due to high leakage current most probably)
    • Reminder:
      • all data taken at 10 MHz
      • trigger was using DPTS
    • First step with Python script on no-beam data to identify hot and RTS pixels
      • remark by Christine, RTS behaviour depends on read-out frequency
      • RTS affect about 5% of the pixels over the 3 submatrices
    • The flow of the analysis is fully ready with Corryvreckan
    • We should target to get some results on June 14th or 21st
      • priority is to obtain SNR distribution for B4 and A4 (for which lab tests were shown by Szymon)
      • Question about impact of RTS on results: need SNR with and without removing the RTS pixels

 

  • Test setup for irradiated sensors, Sergey
    • 2 chips (A4, B4) to be declassified at CERN and will be bring back to IPHC
    • DaqBoard can read only part of the matrix to speed-up the read-out
      • but only starting from 1st pixel (AC-Amp => can mimic other matrices with propoer HV)
    • For the software, Szymon would need some work
      • will have a quick look, then Sergey can work on the debugging
    • About measuring the leakage current, Andrei
      • either directly on HV, if high enough in nA range (not possible for not irradiated sensors)
      • either through decaying shape of pixel signal

 

  • CE-65v2, Andrei
    • all versions (15) were submitted to CERN
      • all same functionalities for all pitch 15, 18, 22.5 µm
    • would welcome a check by others
      • visual inspection by Szymon
      • simulation by ?

 

  • MOSS design, Xiaochao
    • currently generating Liberate file for the matrix to analyse the timing -> deadline 1 week

 

  • MOST design, Szymon
    • system to monitor the biasing by getting the current out
    • then verification on the analogue level
    • probably still other tasks...

 

=> Next meeting Wednesday 15th

 

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