65 nm meeting

Europe/Paris
Bat 20 - uElec (https://cern.zoom.us/j/69600555186?pwd=eVcxUTBnc2J0bWwyQ3RBM0ttZkN6Zz09)

Bat 20 - uElec

https://cern.zoom.us/j/69600555186?pwd=eVcxUTBnc2J0bWwyQ3RBM0ttZkN6Zz09

* MOSS design, Xiaochao, Fred
 - situation with additional metal:
    o design kit being prepared/installed at CERN (6 metals)
    o metal 4 is changed (the addition of new metals is not the only change)
    o PDK will be shared over cliosoft/SOS (in discussion with Pedro)
       => require list of CERN-login of design to access the PDK
    o probably will delay a bit the submission
    o exercise of mock-submission -> rather January than December ?
  - for our block: PE
     o CERN required some modifs (buffers)
     o some additional verifications
     o not impacted by new PDK for additional metals
  - Sur le manpower pour les activités futures de design
     o LPSC: Fatah Rarbi pourrait contribuer à partir de l'an prochain, sujets: ADC (?)
     o IP2I: le retour en 2022...
     ==> nécessité de discuter en amont avec Gianluca puis revenir auprès des groupes Français

 

* CE65++ design, Andrei
  - pad-ring with 3 power domains in the working, to be crosschecked with CERN
  - discussion on various options identified 2 weeks ago
    o Auguste: why not re-introducing 15 um with digital output?
       * reminder that it is not possible to include PE-microcircuit in 15 um (explain MOSS-choice of 18 um)
       * the analogue version has 15 um can be used to study the resolution
       * Remark by Andrei: another amplification design, more compact, is required to allow for
       * note that the exclusion-zone around the diode is 5x5 um2
  - timeline & personpower
    o at least 1 final chip to be ready by end of 2021
    o then all the other variants (~8 circuits) to be ready within first months of 2022
    o Szymon can help if instructed on what to do
  - impact of new PDK?
    o since matrix not yet existing... difficult to say

 

* MOST design, Szymon
  - target to finish before Christmas
  - Szymon's part should be send by mid-December
  - about new metal stack -> not yet there according to Szymon: is that contradicting Fred's news...not clear
      => final choice depends on whether designers can meet the deadline or not

 

* Tests of CE65, Szymon, Serhiy
 - current conclusion
   o node capacitance seems to be small ~2-3 fF
   o other still unknown issues (frequency, noise, negative charge of pixels...)
 - Why don't we see the 6.5 keV peak from 55Fe?
    o seems not compatible with pixel noise
    o suggest to build calibration pixel per pixel
 - About cluster size, currently 3x3
    o suggest to go 5x5 and compare results
 - About negative values of neighbour pixels
    o due to slow signal restoration
    o need to do something about that
  - About the clock read-out
    o no understanding at all about this effect (not expected at all!)
    o Andrei suggests to increase current
  - B1 not seeing anything => probably due to doping
  - For C and D sensors, we need fixed PCBs
 - Test Beam DESY
   o Serhiy leaves on Saturday => sensors should be ready by Friday
   o 2 DAQboards will be
   o Sensor list: A1, A4, B4, plus hopefully D4 if ready
   o irradiated sensors at 100 and 500 Mrad...  not for beamtest

 - Corryvreckan, Yitao
    o working on monitoring
    o will be able to say online whether ref tracks are correlated with CE65
    o require noise runs in order to input noise map to the analysis
       - fallback solution is to use noise maps from lab test

===> Next meeting on Thursday December 9th, at 11 AM (due to WP1.2 https://indico.cern.ch/event/1094135/)

 

 

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