Séminaires
AMchip04: a new generation associative memory chip for HEP applications
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Europe/Paris
1222-RC-08 (LPNHE)
1222-RC-08
LPNHE
Description
The track reconstruction in high-energy physics experiments requires a large online computing power. The Silicon Vertex Tracker (SVT) in CDF and its evolution the FastTracKer (FTK) in ATLAS are two online processors that actually represent the state of the art in track reconstruction at hadron colliders. They are based on a two stage algorithm. The first stage finds low resolution tracks using a pattern recognition algorithm, the second stage refines the first stage result using a algorithm based on a linear fit. The pattern recognition stage is performed in real time by a special content addressable memory, the Associative Memory, specifically designed for HEP applications. I will describe the ideas and physics motivations behind the Associative Memory. I will provide a brief history of the actual VLSI implementations of the Associative Memory, from the first full custom 700 nm chip to the latest 65 nm prototype, the AMchip04. I will describe in more detail the AMchip04 design, development strategy and new innovative features, in particular the introduction of ternary logic cells and the optimizations for low power consumption and high density.