# Program created: 2021_10_08-14-57-54
Commands sent: 35
0	cmd: fe 0 mode after                         
1	cmd: fe fec_enable 1                         
2	cmd: fe fec_enable                           
3	cmd: fe 0 after 0 wrchk 3 0x0 0x0000 0x0000  
4	cmd: fe 0 after 1 wrchk 3 0x0 0x0000 0x0000  
5	cmd: fe 0 after 2 wrchk 3 0x0 0x0000 0x0000  
6	cmd: fe 0 after 3 wrchk 3 0x0 0x0000 0x0000  
7	cmd: fe 0 after 4 wrchk 3 0x0 0x0000 0x0000  
8	cmd: fe 0 after 5 wrchk 3 0x0 0x0000 0x0000  
9	cmd: fe 0 after 6 wrchk 3 0x0 0x0000 0x0000  
10	cmd: fe 0 after 7 wrchk 3 0x0 0x0000 0x0000  
11	cmd: fe 0 after 0 wrchk 3 0x0 0x0101 0x0101  
12	cmd: fe 0 after 1 wrchk 3 0x0 0x0202 0x0202  
13	cmd: fe 0 after 2 wrchk 3 0x0 0x0303 0x0303  
14	cmd: fe 0 after 3 wrchk 3 0x0 0x0404 0x0404  
15	cmd: fe 0 after 4 wrchk 3 0x0 0x0505 0x0505  
16	cmd: fe 0 after 5 wrchk 3 0x0 0x0606 0x0606  
17	cmd: fe 0 after 6 wrchk 3 0x0 0x0707 0x0707  
18	cmd: fe 0 after 7 wrchk 3 0x0 0x0808 0x0808  
19	cmd: fe 0 after 0 read 3                     
20	cmd: fe 0 after 1 read 3                     
21	cmd: fe 0 after 2 read 3                     
22	cmd: fe 0 after 3 read 3                     
23	cmd: fe 0 after 4 read 3                     
24	cmd: fe 0 after 5 read 3                     
25	cmd: fe 0 after 6 read 3                     
26	cmd: fe 0 after 7 read 3                     
27	cmd: fe 0 after 0 wrchk 3 0x0 0x0000 0x0000  
28	cmd: fe 0 after 1 wrchk 3 0x0 0x0000 0x0000  
29	cmd: fe 0 after 2 wrchk 3 0x0 0x0000 0x0000  
30	cmd: fe 0 after 3 wrchk 3 0x0 0x0000 0x0000  
31	cmd: fe 0 after 4 wrchk 3 0x0 0x0000 0x0000  
32	cmd: fe 0 after 5 wrchk 3 0x0 0x0000 0x0000  
33	cmd: fe 0 after 6 wrchk 3 0x0 0x0000 0x0000  
34	cmd: fe 0 after 7 wrchk 3 0x0 0x0000 0x0000  
Responses got: 35
0	code:  0 resp: 0 Tdcm(2) Fem(00) Reg(0) <- 0x400
1	code:  0 resp: 0 Tdcm(2) Fem(00) Reg(1) <- 0x40000
2	code:  0 resp: 0 Tdcm(2) Fem(00) Reg(1) = 0x2048000 (33849344) FEC_Enable: 1
3	code:  0 resp: 0 Tdcm(2) Fem(00) After(0) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
4	code:  0 resp: 0 Tdcm(2) Fem(00) After(1) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
5	code:  0 resp: 0 Tdcm(2) Fem(00) After(2) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
6	code:  0 resp: 0 Tdcm(2) Fem(00) After(3) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
7	code:  0 resp: 0 Tdcm(2) Fem(00) After(4) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
8	code:  0 resp: 0 Tdcm(2) Fem(00) After(5) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
9	code:  0 resp: 0 Tdcm(2) Fem(00) After(6) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
10	code:  0 resp: 0 Tdcm(2) Fem(00) After(7) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
11	code:  0 resp: 0 Tdcm(2) Fem(00) After(0) Reg(3) <- 0x0 0x101 0x101 (1 chip verified)
12	code:  0 resp: 0 Tdcm(2) Fem(00) After(1) Reg(3) <- 0x0 0x202 0x202 (1 chip verified)
13	code:  0 resp: 0 Tdcm(2) Fem(00) After(2) Reg(3) <- 0x0 0x303 0x303 (1 chip verified)
14	code:  0 resp: 0 Tdcm(2) Fem(00) After(3) Reg(3) <- 0x0 0x404 0x404 (1 chip verified)
15	code:  0 resp: 0 Tdcm(2) Fem(00) After(4) Reg(3) <- 0x0 0x505 0x505 (1 chip verified)
16	code:  0 resp: 0 Tdcm(2) Fem(00) After(5) Reg(3) <- 0x0 0x606 0x606 (1 chip verified)
17	code:  0 resp: 0 Tdcm(2) Fem(00) After(6) Reg(3) <- 0x0 0x707 0x707 (1 chip verified)
18	code:  0 resp: 0 Tdcm(2) Fem(00) After(7) Reg(3) <- 0x0 0x808 0x808 (1 chip verified)
19	code:  0 resp: 0 Tdcm(2) Fem(00) After(0) Reg(3): 0x0 0x101 0x101
20	code:  0 resp: 0 Tdcm(2) Fem(00) After(1) Reg(3): 0x0 0x202 0x202
21	code:  0 resp: 0 Tdcm(2) Fem(00) After(2) Reg(3): 0x0 0x303 0x303
22	code:  0 resp: 0 Tdcm(2) Fem(00) After(3) Reg(3): 0x0 0x404 0x404
23	code:  0 resp: 0 Tdcm(2) Fem(00) After(4) Reg(3): 0x0 0x505 0x505
24	code:  0 resp: 0 Tdcm(2) Fem(00) After(5) Reg(3): 0x0 0x606 0x606
25	code:  0 resp: 0 Tdcm(2) Fem(00) After(6) Reg(3): 0x0 0x707 0x707
26	code:  0 resp: 0 Tdcm(2) Fem(00) After(7) Reg(3): 0x0 0x808 0x808
27	code:  0 resp: 0 Tdcm(2) Fem(00) After(0) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
28	code:  0 resp: 0 Tdcm(2) Fem(00) After(1) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
29	code:  0 resp: 0 Tdcm(2) Fem(00) After(2) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
30	code:  0 resp: 0 Tdcm(2) Fem(00) After(3) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
31	code:  0 resp: 0 Tdcm(2) Fem(00) After(4) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
32	code:  0 resp: 0 Tdcm(2) Fem(00) After(5) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
33	code:  0 resp: 0 Tdcm(2) Fem(00) After(6) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)
34	code:  0 resp: 0 Tdcm(2) Fem(00) After(7) Reg(3) <- 0x0 0x0 0x0 (1 chip verified)

