65 nm meeting

→ Europe/Paris
Bat 20 - uElec (https://cern.zoom.us/j/69600555186?pwd=eVcxUTBnc2J0bWwyQ3RBM0ttZkN6Zz09)

Bat 20 - uElec

https://cern.zoom.us/j/69600555186?pwd=eVcxUTBnc2J0bWwyQ3RBM0ttZkN6Zz09
Cacher
  • MOSS design
    • Mock-up submission was sent this week (situation with new metal layers unclear)
    • last meeting before Xmas break:
      • check-list asked on our designed PE
      • timing verification with pixel array (FE + read-out but without periphery) to start
        (include Jean to some level when power concerned)
    • reminder on our PE: only 3 metal used
    • regarding the design of the whole sensor: large work on simulation on-going

 

  • MOST design
    • no real fresh news from Xmas break, mock-up submission reached
    • our design part not really affected by new metal layers
    • SOS directory access set-up (for MOSS and will be soon functional for MOST)
    • on-going work : verification on pulsing part

 

  • CE-65++ design
    • one chip (matrix and core done but not yet verified) entered the mock-up submission
      • that's the most complicated (AC-coupled diode) one from design point of view
    • full metal stack (including the one for pad) used in design
    • this chip is the based for the rolling-shutter family variants
      • need test results from CE-65 to make variant choices (front-end from CE-65 and from MOSS)
      • need finalization, e.g. pad-ring
    • still to develop 2 chips (for other family variants) from that basis (many parts re-used)
      • BUT same pad-ring for all families
    • About the time and method to define the variants
      • we discuss internally during Thursday meetings and then make proposals to CERN
      • Walter already agreed on our various proposals but require proof from test about the functional variants
      • we should have refined proposal by end of January in view of our test results

 

  • CE-65 tests
    • need someone dedicated to conduct systematic tests
      • critical for submission of CE-65++
    • Szymon tried to tackle the issues
      • dependence on clock read-out
      • negative undershoot after signal
    • About Undershoot
      • culprit may be the OpAmp for the buffered signal on the carrier PCB
      • may be mitigated with a lower resistance,
      • first tests are promising on scope BUT undershoot still present on spectra
      • => potential similar issue on the proxy PCB (suggested by scope screenshots)!
        • change on-going by uTech... waiting
      • suggestion by Andrei that it might be a feature of the Amplifier
        • would require investigation of all differential signals => looks difficult to do, need help!!
      • suggestion by Kimmo
        • study the issue at lower frequency, (only possibility is 20 MHz)
    • No idea how to clarify the clock read-out issue
      • new ideas & discussion needed on this
    • Szymon and Jerome should gather the present results (40 Mhz) into a document
    • Need to prepare doc for Andrei to be able to use the system and investigate: not before next week
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